1. Field of the Invention
The present invention relates to reset control circuit and reset control method of a circuit system, and more particularly to reset control circuit and reset control method for resetting by issuing a reset signal to the system corresponding to a reset request signal, in reset operation in case of abnormality.
2. Description of the Related Art
A circuit system is often used in severe conditions such as unstable supply voltages and large changes in ambient temperature.
A typical example is microcomputer system mounted on an automobile known as car-mount microcomputer system. In the battery for supplying electric power to this car-mount microcomputer system, for example, when driving a self-starter for starting up the engine, the voltage drops significantly, and the supply voltage to be supplied to the system also declines. On the other hand, the automobile compartment may be exposed to high temperature in midsummer. In such circumstances, when the supply voltage is lower than the rated voltage or the ambient temperature is higher than the rated temperature, the car-mount microcomputer system may fail to operate normally. Even in such abnormal state, the car-mount microcomputer system is demanded at least to save the data stored in the RAM or register. Hence, the reset control circuit used in the car-mount microcomputer system is often designed to take in a reset request signal and generate a reset signal in synchronization with clock signal, when commanded from other system or outside, or when abnormal state of supply voltage or ambient temperature is detected.
Some systems of car-mount microcomputer system are designed to operate at lower clock frequency as compared with the reset response requested with respect to detection of abnormal state. Further, such reset operation of the system maybe synchronized with the clock signal.
In the reset control circuit used in such systems, since the reset operation is conducted by using a low clock frequency, the problem that the system cannot be reset right after detection of abnormality occurs. To solve such problem, it may be considered to design a reset control circuit capable of changing over the clock frequency to be supplied in the system simultaneously with reset operation.
The circuit disclosed in Japanese Patent No. 3119628 comprises first clock generating means for generating and issuing a clock signal to be supplied to a clock synchronous type semiconductor storage device in normal operation, and second clock generating means at lower speed. It further comprises a reset circuit for generating a power-on reset signal for a specified period from supply of power by monitoring the power source potential, and a clock changeover circuit for selecting and issuing either one of the output of the first clock generating means and the output of the second clock generating means, depending on the power-on reset signal. The clock changeover circuit supplies the output of the second clock generating means as clock signal to the synchronous type semiconductor storage device when the power-on reset signal is activated. That is, the clock signal supplied to the clock synchronous type semiconductor storage device activates the power-on reset signal, and also changed over from the output of the first clock generating means to the output of the second clock generating means.
Accordingly, by using the control circuit of Japanese Patent No. 3119628, it may be considered to compose a reset control circuit for changing over the output of the clock signal from the first clock generating means to the second clock generating means when activating the reset signal. In this case, reverse to the case of Japanese Patent No. 3119628, the second clock generating means is means for issuing a higher frequency than the first clock generating means. Thus, at the time of detection of abnormal state, the system can be reset more promptly by resetting by using a clock signal of higher frequency.
However, in the reset control circuit for taking in the reset request signal in synchronization with the clock signal, when the frequency of clock signal is low or when the clock signal is stopped, it takes a longer time until the reset request signal is taken in, or the reset request signal may not be taken in.
Or, in a system of resetting synchronously with clock signal, suppose the clock signal is a lower clock frequency as compared with the reset response requested to detection of abnormal state. In this case, as mentioned above, it may be considered to compose a reset control circuit by making use of the circuit disclosed in Japanese Patent No. 3119628. Even by using this means, however, the following problems occur.
By detection of abnormal state, when the clock signal is changed over by activating the reset signal and resetting, suppose it is in the midst of writing cycle of RAM or register. At this time, since the internal bus is initialized, the writing data entered in the RAM or the like is also initialized. In the RAM, moreover, the content of the writing data entered at the moment of resetting is written. That is, the initialized data or unspecified data in the midst of initializing is written in the RAM, which is different from the content intended to be written in, and problems are caused.